In FPGA-based development and implementation, the development cost is largely dependent on the price of the FPGA device on which a designed circuit is implemented. The price of an FPGA varies depending on the FPGA device vender and the circuit size. A large-scale FPGA utilizing a state-of-art technology tends to be very expensive. A designer taking part in the FPGA-based development process makes every effort such as to use a prior-generation FPGA device or a small-scale FPGA device for the purpose of reducing cost as much as possible. Because of this, a circuit design process requires the utilization of FPGA resources to the maximum extent.
An FPGA circuit design process typically utilizes an RTL (register transfer level)-based design that is independent of the choice of technology and the choice of a vendor. Circuit portions other than the RAM (random access memory) can be efficiently implemented on an FPGA through CAD (computer aided design)-based optimization and the like.
An FPGA device has RAMs (i.e., block RAMs) implemented therein, a number of which is specific to each FPGA device. Implementation of a given circuit design may require a larger number of RAMs than the number of block RAMs provided in the FPGA device to be used. To cope with such a situation, a higher-grade FPGA device having a larger number of block RAMs may be used, or external RAMs may be additionally used. The use of a higher-grade FPGA device, however, directly leads to a cost increase. Further, the use of an external RAM may require changes in the RTL design and in the printed circuit board, resulting in an increase in the development cost.
[Patent Document 1] Japanese Laid-open Patent Publication No. 2007-207042
[Patent Document 2] Japanese Laid-open Patent Publication No. 2000-207274
[Patent Document 3] Japanese Laid-open Patent Publication No. 2004-178056